1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method for the same, and in particular to a semiconductor memory device, which includes a memory transistor having a charge storage layer and a control gate, and a manufacturing method for the same.
2. Description of the Related Art
Non-volatile memories represented by a NAND-type flash memory are used in a variety of fields such as in computers, communications, measurement equipment, automatic control apparatuses, consumer electronics for private use and the like as compact data recording media having large capacities. Accordingly, demand for non-volatile memories having large capacities at low costs is very high.
However, the capacity of a so-called planar-type memory, where memory cells are formed in a plane on a semiconductor substrate, is restricted by the minimum processing dimensions (feature size) that are the resolution limit of the photolithographic technology. Under such circumstances, multi-value technology and three-dimensional technology of a memory cell are respectively desired as the technologies for achieving the integration in the next generation without depending on an improvement of the photolithographic technology.
Multi-valued memory cells are roughly divided into a threshold value control type wherein a memory cell is made to have three or more threshold values and a charge storage region divided type where the region for holding a charge is divided within one memory cell so that each divided region independently stores a charge. A floating gate type, for example, is included in the former threshold value control type, and an NROM type (see, for example, Japanese Unexamined Patent Publication No. 2001-77220), a divided floating gate type (see, for example, Extended Abstract of the 2000 International Conference on Solid State Devices and Materials, Sendai, 2000, pp.282-283 and Japanese Patent No. 2870478) and the like are known as examples of the latter charge storage region divided type.
An NROM type memory cell which is a charge storage region divided type is shown in FIG. 153. Here, in FIG. 153 a semiconductor substrate is denoted as 1, an element isolation region is denoted as 50, an element region is denoted as 15, an impurity diffusion layer is denoted as 12, a silicon oxide film is denoted as 18, a silicon nitride film is denoted as 17, a silicon oxide film is denoted as 20, and a control gate is denoted as 60. In this memory cell the charge storage layer is formed of oxide film/nitride film/oxide film (ONO film) and, thereby two charge holding regions are created in one memory cell so that it becomes possible to store two-bit data in one memory cell.
In addition, FIGS. 154 and 155 show floating gate division type memory cells which are a charge storage region divided type. In FIGS. 154 and 155 a semiconductor substrate is denoted as 1, an element isolation insulating film is denoted as 2, first diffusion regions are denoted as 3, second diffusion regions are denoted as 4, a first insulating film is denoted as 6, first floating gate electrodes are denoted as 7, second floating gate electrodes are denoted as 7a, a second insulating film is denoted as 8, control gate electrodes are denoted as 9 and an insulating film is denoted as 10. Here, FIG. 155 shows a cross section of the memory cells along III-IV of FIG. 154. In these memory cells the floating gate in one memory cell is divided into the first floating gate 7 and the second floating gate 7a and, thereby it becomes possible to store two-bit data in one memory cell.
Thus a capacity greater than that of the planar type memory is secured in the same processing dimensions in either of the above described multiple value technologies, so as to overcome the capacity restriction due to the resolution limit of the photolithographic technology.
On the other hand, a memory cell is placed in the direction perpendicular to the substrate according to the three-dimensional technology of a memory cell and, thereby a capacity greater than that of the planar type memory is implemented in the same processing dimensions in the same manner as in the multiple value technology. Here, the precision required for the control of the amount of charge is the same as in the planar type memory according to this three-dimensional technology while the number of memory cells aligned in the direction perpendicular to the substrate is increased and, thereby an increase in the capacity can be implemented.
According to the above described multiple value technology of a memory cell, the greater the amount of data stored in one memory cell in the threshold value control type, the higher the precision required in the charge amount control technology. Accordingly, the operational speed is lowered. In addition, there is a problem in the charge storage region divided type where data that exceed two bits cannot be stored in one memory cell. Furthermore, bit lines and source lines are respectively formed of impurity diffusion layers in the charge storage region divided type and, therefore, a punch through phenomenon is introduced in the planar cell array when the distance between the respective impurity diffusion layers is reduced together with the reduction of the minimum processing dimensions in the manufacturing process or due to the reduction of the design rule in the manufacturing process. This hinders the scaling down and is not appropriate for an increase in the integration.
In addition, in the three-dimensional technology, the more the number of layers of a memory cell is increased, the greater becomes the number of manufacturing steps causing an increase in the manufacturing costs, an increase in the period of time for the manufacture and a decrease in the yield. Furthermore, in a manufactured memory cell, dispersion occurs in the cell characteristics due to the difference in the film quality of the tunnel film caused by thermal hysteresis at each stage and due to the difference in the profile of the impurity diffusion layers.